Memory Team - Physical Design Engineer

Position Summary

Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs

Role and Responsibilities

• Hands on experience doing physical design and timing closure of complex blocks and full-chip designs
• Should have strong understanding of timing, power and area trade-offs and optimization of PPA
• Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities
• Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
• Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking
• Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturabilit...