Memory Subsystem Verification Engineer - SystemVerilog/UVM

A leading semiconductor company is seeking a Memory Subsystem Design Verification Engineer in Markham, Canada. This role will involve designing and implementing verification environments for memory subsystems using SystemVerilog and UVM methodologies. Candidates should have strong proficiency in C/C++, verification experience with various methodologies, and a solid academic background in relevant engineering fields. The position offers a competitive salary range and is part of a diverse and inclusive workplace.
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