Memory PHY RTL Design Lead — Drive DDR/IP Innovation

A leading semiconductor company is seeking a Memory PHY RTL Design Lead in Markham. This role involves owning RTL design for high-speed LPDDR and DDR IPs, collaborating closely with cross-functional teams, and providing mentorship to junior engineers. Ideal candidates will have deep knowledge of DDR PHY/controller architecture, experience with Verilog/SystemVerilog, and a strong background in digital design engineering. The role offers competitive compensation and a dynamic work environment focused on innovation.
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