Lead Static Timing Analysis (STA) Engineer

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Lead Static Timing Analysis (STA) Engineer

• Bangalore, India
• 10+
• Full-Time
  
  

We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.

Key Responsibilities

• Own and drive timing closure for multiple blocks or full-chip designs from synthesis through tape-out.
• Develop and maintain timing constraints (SDC) for synthesis, place-and-route, and sign-off flows.
• Perform setup, hold, recovery, and removal analysis using industry-standard STA tools.
• Analyze timing reports and debug violations, providing guidance to physical design, RTL, and DFT teams.
• Work closely...