Lead FPGA IP Design Engineer RTL - Full Lifecycle

Silicon One in Bayan Lepas, Penang, Malaysia is seeking a high-caliber IP Design Engineer to join our team. You will drive full lifecycle FPGA IP development from architecture to RTL implementation for networking products.

Candidates should have a Bachelor’s degree or higher in Electronic Engineering or related fields and at least 5 years of hands-on Verilog/VHDL experience, along with proficiency in Vivado/ISE/Quartus and RTL simulation tools.