Job Description

Job Summary

Join a dynamic semiconductor team to design advanced test structures and develop scalable layout solutions using cutting-edge tools.

Responsibilities
  • Develop, maintain, and optimize complex parameterized cells (PCells) for large-scale layout generation.
  • Prepare device tape-out deliverables and coordinate with foundry design kits (FDK).
  • Conduct device test structure data collection and analysis to support development activities.
Requirements
  • Degree in Physics, Electrical Engineering, or related disciplines is preferred.
  • 3 - 10 years of hands‑on experience in custom layout design.
  • Proficiency in layout tools such as Laker or Cadence Virtuoso.
  • Strong programming skills in SKILL/SKILL++, Tcl, C/C++, or similar scripting languages for EDA environments.
  • Proven ability to develop, debug, and support complex PCells and batch layout generation.
  • Solid understanding of...

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