Layout Engineer

We are looking for a highly skilled Memory Layout Engineer with strong expertise in advanced node technologies to support high‑performance semiconductor designs. The ideal candidate will have hands‑on experience in memory layout development, physical verification, and top‑level integration across SRAM and other memory architectures on TSMC FinFET processes .

Key Responsibilities

• Design and implement custom layouts for memory blocks , including
• Develop and optimize layouts for critical memory components such as
• Perform top‑level memory integration , ensuring seamless assembly of memory macros within SoC environment
• Execute and resolve physical verification checks , including Density check
• Drive layout cleanup and signoff closure , ensuring high‑quality tapeout readiness
• Analyze and mitigate IR drop and EM (Electromigration) issues in memory layout
• ...