Job Description

Responsibilities

  • 4+ years experience in semiconductor industry
  • Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.
  • Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.
  • Clear understanding of ASIC design flow
  • Solid analytical, synthesis and problem solving skills


Skills Required
RTL, Uvm, System Verilog

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