Job Description

Job Details

Job Description:

Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

Key Responsibilities

  • Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
  • Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
  • Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
  • Develop verification components, including drivers, monitors, scoreboards, and checkers.
  • Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
  • Execute simulation...

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