IP Design Verification Engineer

Job Title: IP Design Verification Engineer

Experience: 7 – 15 Years

Location: Bangalore

Job Overview

We are looking for an experienced IP Design Verification (IP DV) Engineer with strong expertise in SystemVerilog/UVM-based verification of high-speed IPs and interconnect protocols. The ideal candidate should have hands-on experience in building scalable verification environments, coverage closure, and working in a multi-national setup.

Key Responsibilities

• Develop and execute verification plans for complex IPs.
• Build reusable verification environments using SystemVerilog (SV) / UVM.
• Perform IP verification for high-speed serial and interconnect protocols.
• Drive coverage closure including:
• Code Coverage
• Functional Coverage
• Toggle Coverage
• Create and maintain technical documentation:
...