IC Verification Engineer

Key Skills: SystemVerilog, UVM Methodology, SV/UVM Testbench, OVM/UVM Verification Environments, Functional Coverage, Regression Debugging, PCIe, AXI4, I2C

Roles & Responsibilities

• Architect and develop scalable and reusable testbench environments using advanced verification methodologies.
• Drive verification test plans for Block/Core/SOC features and define functional coverage requirements.
• Build pseudo-random tests to ensure full functional coverage and achieve verification closure.
• Debug regression failures, analyze functional coverage gaps, and optimize verification environments.
• Collaborate with team members and mentor junior engineers to enhance team expertise.
• Innovate verification approaches to efficiently validate the Design Under Test (DUT).
• Document verification strategies, test plans, and verification environment details comprehensively.
• Continuously dr...