Job Description
Emulation Engineer
Experience : 4-5 years
Location : Hyderabad
4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)
Working knowledge of System Verilog & Verilog language semantics and compilation flows
Solid understanding on SOC architecture and AXI protocol
Good communication skills and team collaboration
Interested,please share your updated resume to [HIDDEN TEXT]
Skills Required
Soc Architecture, Verilog, Palladium, Cadence, Synopsys, System Verilog
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