Job Description

Responsibilities

  • Design architecting and trade-off analysis

  • RTL coding and verification

  • Memory Controller + PHY integration and verification

  • Customer delivery and support

    • Qualifications

    Strong System Verilog/Verilog RTL design expertise


  • Questa/Incisive/VCS simulator experience

  • Python/Perl/Tcl scripting experience

  • Significant ASIC and/or FPGA design experience

  • Ability to learn quickly and work independently

  • Solid communication and project management skills

  • 5+ years of logic design experience

  • BSEE

    • Definite Plus:


  • ASIC synthesis, timing constraint, CDC/RDC experience

  • Verification experience

  • Memory (HBM, GDDR, LPDDR, DDR) expertise

  • AMBA AXI or CHI design experience

  • Located in the Hillsboro, Oregon area

    • Training:

  • Provided as needed

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    Job Details

    Location
    Hillsboro, Oregon, United States
    Job Type
    Full-time
    Category
    Engineers
    Posted Date
    February 19, 2026
    Deadline
    March 31, 2026