Job Description

About the Role

Verification Engineer with over 4 years of experience in Gate-Level Simulation (GLS).

Skilled in UVM, SystemVerilog, and industry-standard verification methodologies.

Responsibilities

  • Strong in debugging, timing analysis, and simulation to ensure design accuracy and performance.

Required Skills

  • HDL/HDVL: Verilog, System Verilog
  • Tools: Synopsys VCS, Verdi, DVE GLS
  • Expertise: Zero Delay (ZD), SDF, Power-Aware GLS (PAGLS)

Preferred Skills

  • Others: Low-Power Verification, RTL Debug, UVM Environments


Skills Required
SDF, gls , Verilog, Uvm, systemverilog, Hdl

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