Frontend Design Implementation Lead

Location: Bengaluru, India Experience: 10–15 years Industry: Semiconductors | AI | Networking | ASIC Design

Role Overview

As the Synthesis & LEC Lead, you will be the bridge between high-level RTL

architecture and physical reality. In the world of high-performance AI SOCs, the RTL-to-Netlist

phase is where performance is won or lost. You will hold end-to-end ownership of logical and

physical synthesis, and formal verification, ensuring our chips achieve industry-leading Power,

Performance, and Area (PPA) targets while maintaining 100% logical integrity.

Key Responsibilities

Synthesis & PPA Optimization

● End-to-End Ownership: Define and drive the synthesis strategy, from initial RTL

handoff through complex gate-level netlist generation and timing closure.

● Low-Power Implementation: Drive front-end low-power optimization using UPF,

ensuring sophisticated power-gating and multi-voltage s...