Job Description

JD

  • Strong in hands on lab-based silicon validation
  • Hands-on with high-speed protocols
  • FPGA RTL + Verilog and C
  • Experienced in board-level debug experience (Mandatory)

This is not a pure FPGA RTL design role. kindly don't share with just FPGA experience

This is a FPGA validation + lab debug role.

Ready to Apply?

Take the next step in your AI career. Submit your application to ACL Digital today.

Submit Application