FPGA IP Design Engineer: RTL, Synthesis & Tape-Out

Silicon One in Bayan Lepas, Penang, Malaysia, is seeking a high-caliber IP Design Engineer to drive the full development lifecycle of FPGA IP solutions for next-generation networking products. You will contribute from architecture definition to RTL implementation.

The role demands strong Verilog/VHDL expertise, hands-on experience with Vivado/ISE/Quartus, and a deep understanding of timing closure, DFT, and front-end design. Collaboration across teams and mentoring FAEs are part of the job.