Job Description
Job Details
Job Description:
As an FPGA IO Front End Design Engineer, you will be responsible to define & implement the design (micro-architecture, BMOD/RTL, linting, CDC, SDC, UPF/power gating) of high speed IO design in cutting edge technology node.
You will work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure. You will need to work on post Silicon debug/characterization support of the designs.
Qualifications
BS/MS or PhD in Electronics Engineering with minimum of 5 years of IO Front End frontend experience
Strong in communication, leadership, investigation, problem solving & analytical skill
Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT. Knowledge scripting desirable
Job Type
Regular
Shift
Shift 1 (Malaysia)
P...
Job Description:
As an FPGA IO Front End Design Engineer, you will be responsible to define & implement the design (micro-architecture, BMOD/RTL, linting, CDC, SDC, UPF/power gating) of high speed IO design in cutting edge technology node.
You will work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure. You will need to work on post Silicon debug/characterization support of the designs.
Qualifications
BS/MS or PhD in Electronics Engineering with minimum of 5 years of IO Front End frontend experience
Strong in communication, leadership, investigation, problem solving & analytical skill
Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT. Knowledge scripting desirable
Job Type
Regular
Shift
Shift 1 (Malaysia)
P...
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