Job Description

Our company is developing a hardware‑in‑the‑loop (HIL) framework that connects MATLAB models to a Zynq‑based FPGA platform via Ethernet. This setup enables near real‑time testing of RF/PHY functionality and allows MATLAB algorithm developers to validate their work without waiting for full hardware integration. The goal is to build a lightweight, OS‑less (or minimal) FPGA system that can exchange packets efficiently with MATLAB and provide direct access to FPGA registers/ internal signals through Ethernet. This HIL setup will accelerate our development cycle and serve as a reusable platform for future projects. 

Your Mission 

As a Master’s thesis student, you will: 

  • Develop a MATLAB FPGA Ethernet communication interface for transmitting raw samples and control messages. 
  • Implement bare‑metal or minimal runtime on Zynq to avoid OS overhead and ensure deterministic packet flow. 
  • Explore the use of a secondary SFP/Ethernet interface for debug pa...

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