Job Description

Socode are seeking a hands-on RTL FPGA engineer who will be building a real-time 12G-SDI video pipeline on Xilinx Zynq UltraScale+ for a 9-month contract in Cambridge, UK.


You will:

  • Implement uncompressed UHD 12G-SDI capture and transmit (SMPTE standards)
  • Design full-frame alpha-blended compositing in programmable logic
  • Build AXI4-Stream video pipelines with VDMA/DDR buffering
  • Configure and tune GTY/GTX transceivers for 12G data rates
  • Close timing in Vivado at UHD bandwidths
  • Develop simulation testbenches and perform hardware validation
  • Measure and optimise deterministic, sub-frame latency

Required experience:

  • Xilinx Vivado and Zynq PS/PL architecture
  • 3G/6G/12G-SDI implementation in FPGA
  • Frame/line buffer design and high-bandwidth DDR interfaces
  • Real-time, low-latency video systems


Broadcast video FPGA ex...

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