Job Description

Formal Verification Engineer, Platform, IP, CompIP

_corporate_fare_ Google _place_ Bengaluru, Karnataka, India

**Mid**

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
+ 8 years of experience with formal verification in SystemVerilog and SystemVerilog Assertion.
+ Experience leading formal verification for IPs/sub-systems.

**Preferred qualifications:**

+ Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
+ Experience in Formal Property Verification (FPV) with a proven track record of developing comprehensive property suites for high-complexity designs.
+ Experience in low-power design verification.

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