Digital Verification Engineer II — RTL/UVM

A leading technology company in Montreal seeks a Design Engineer II focused on digital RTL verification. The ideal candidate will have a Bachelor’s degree in Electrical/Computer Engineering and expertise in verification methodologies. Responsibilities include developing reusable verification components and communicating with teams regarding project progress. Candidates should have familiarity with SystemVerilog UVM and various scripting languages. This position requires a self-starter attitude and the ability to work collaboratively across disciplines.
#J-18808-Ljbffr