Job Description
Develop test plan from specification and architect system level verification environments.
Develop and maintain UVM-based testbenches for block-level and subsystem-level verification
Write constrained-random stimulus, scoreboards, monitors, and coverage models in SystemVerilog
Contribute to regression infrastructure, continuous integration flows, and internal verification methodology
Drive functional and code coverage closure; analyze coverage holes and add targeted tests
Integrate and configure VIP (Verification IP) for standard protocols
Support FPGA-based prototyping and pre-silicon bring-up with validation test suites
Execute RTL/Gate level simulations and analyze results.
Contribute to design/verific...
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