Job Description
Responsibilities:
- Independently handling Block level PnR implementation with industry-standard tools.
- Responsible for planning and executing all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to closure.
- Ownership of digital sub-blocks/chip level (specification and implementation).
- Definition of new test cases similar to product definition and for designing significant blocks of chip, including chip architecture and chip top integration, with a focus on improving Quality of Design System.
- Develop and execute QA test plans, verification methodology & test strategies for analog block/chip level to maximize the coverage of features/methodology supported in the technologies/Design Flows.
- Responsibility for the setup and running of test cases, analyzing failures, and bug fix validation and verificatio...
Ready to Apply?
Take the next step in your AI career. Submit your application to UST today.
Submit Application