DFT & STA Technical Lead — Timing & Validation

Cisco Systems, Inc. is seeking a detail-oriented DFT Timing Engineer to shape timing constraints and validate SDC flows for advanced ASIC design.

You will collaborate across teams, analyze timing data, and help define robust STA methodologies for high-assurance silicon. Responsibilities include developing constraints at multiple hierarchy levels, validating timing paths in test modes, and contributing to SDC, CDC checks, and tooling optimization.