Job Description

  •  Perform
    ATPG pattern generation including SSA /Transition/RSQ Path Delay and IDDQ
    pattern using Siemens Tessen tools  
  •  Perform
    ATPG verification and simulation playback using Synopsys/ Cadence simulator
  • Strong
    Analytical mindset and simulation debug capabilities to resolve simulation
    mis -match
  • Good
    design knowledge needed that can help improve the test coverage the low
    coverage of a design 
  • Deliver
    high quality ATE patterns for production ATE testing
  • test pattern support to ATE engineering team for First Proto bring up and
    failure analysis in the use of ATPG test and scan/debug features


Requirements

  • Bachelor degree or equivalent in Electrical or
    Computer Engineering
  • 3 to
    5 years DFT working experience

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