Job Description

  • Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra -low power SoC based on subthreshold operation using standard EDA tools.
  • Develop and implement low -power DFT architecture and infrastructure.
  • Generate structural test vectors, analyse, and improve coverage, test time and test cost.
  • Perform pre/post -layout scan and MBIST simulations.
  • Work with designers on STA, physical, power and logical issues related to DFT.
  • Work with test engineers to bring up test vectors on silicon.


Requirements

Specific Experience

  • BS/MS in ECE/EE and at least 7 years of experience in DFT implementation.
  • Skilled in different types of DFT structures, including scan (Stuck -At, At -Speed, Path -Delay), scan compression, boundary scan and MBIST.
  • Experience in creating and implementing hierarchical...