Job Description
Experience : 4+years
Location : Bangalore
Job Description
Will be responsible for Designing and Implementing DFT techniques.
Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.
Test Modes implementation and verification, scan insertion including on-chip compression.
Implementing, integrating and verifying memory BIST and boundary scan.
ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF).
Basic understanding of complete SOC design and flow.
Cross functional teams interaction for issue resolution.
Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability.
Hiring candidate with these specific personal characteristic and qualifications.
Mento...
Location : Bangalore
Job Description
Will be responsible for Designing and Implementing DFT techniques.
Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.
Test Modes implementation and verification, scan insertion including on-chip compression.
Implementing, integrating and verifying memory BIST and boundary scan.
ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF).
Basic understanding of complete SOC design and flow.
Cross functional teams interaction for issue resolution.
Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability.
Hiring candidate with these specific personal characteristic and qualifications.
Mento...
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