Job Description

We are looking for a DFT Engineer to work with cross‑functional teams on implementing and verifying advanced test features in complex IPs, subsystems, and SoCs.

Key Responsibilities:

• Implement DFT features including scan insertion, ATPG, memory BIST, IO BIST, and test access mechanisms.

• Develop and enhance methodologies to verify DFT features across IPs and SoCs.

• Collaborate with design and verification teams to drive ATPG coverage closure and ensure smooth DFT signoff.

Job Complexity:

This role may involve:

• Working under general supervision with established procedures and solving straightforward problems, or

• Working with broader discretion to solve more complex challenges depending on experience.

Experience: 4+ years

Locations: Hyderabad/Bangalore/Pune/Chennai/Noida/Ahmedabad

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