DFT Engineer

Key Responsibilities:
Define and implement SoC-level DFT architecture for large and complex designs.
Develop, integrate, and support Scan & ATPG, MBIST, BSCAN, and IJTAG
Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
Drive pre-silicon DFT sign-off , including DRC closure and coverage targets.
Support post-silicon debug, failure analysis, and yield learning.
Collaborate with RTL, verification, physical design, and silicon teams
Must-Have Skills:
7–10 years of hands-on experience in SoC DFT.
Strong expertise in Scan, ATPG, MBIST.
Experience with pre-silicon validation and post-silicon debug.
Strong problem-solving and debugging skills .
Ability to work effectively in a cross-functional engineering environment
Good-to-Have Skills:
Scripting experience (TCL,Perl, Python, or equivalent) for flow automation and analysis.
Experience with IP-level DFT integration and reuse.
Exposure to low-power DFT...