Job Description

We are hiring a DFT Engineer with strong expertise in scan-stitching and ATPG, with hands-on experience in the Tessent ATPG tool. This role focuses on improving test coverage, debug, and DFT rule compliance across ASIC designs.


  • Hands-on experience in scan-stitching and scan architecture concepts.
  • Strong experience in ATPG flows, pattern generation, and debug.
  • Solid working knowledge of Tessent ATPG.
  • Experience using SpyGlass-DFT for rule checks and analysis.
  • Ability to debug ATPG issues, scan DRC violations, and coverage gaps.


Play a key role in strengthening silicon testability and achieving robust coverage closure.


Regards,

Karthik Kumar

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