Design Verification

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI,

• Experience Level:

5-15 years 

• Education Requirements:

B.Tech/M.Tech in ECE, EEE

• Minimum Qualifications:
• Develop and signoff on test plans and test cases
• Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture
• strong knowledge of Verilog, System Verilog, UVM, C/C++
• Experience in usage of assertions, constrained random generation, functional/code coverage.