Job Description
Job Title: Design Verification Engineer (ASIC / SoC)
Level: Mid-Level
Experience: 4–6 Years
Location: Bengaluru
Employment Type: Full-time
Job Summary
We are looking for a Design Verification Mid-Level Engineer with strong hands-on experience in SystemVerilog and UVM to contribute to IP and SoC verification projects. The role focuses on building verification components, developing test cases, debugging complex failures, and achieving coverage goals in collaboration with senior engineers and design teams.
Key Responsibilities
Level: Mid-Level
Experience: 4–6 Years
Location: Bengaluru
Employment Type: Full-time
Job Summary
We are looking for a Design Verification Mid-Level Engineer with strong hands-on experience in SystemVerilog and UVM to contribute to IP and SoC verification projects. The role focuses on building verification components, developing test cases, debugging complex failures, and achieving coverage goals in collaboration with senior engineers and design teams.
Key Responsibilities
- Develop and enhance UVM-based verification environments, including drivers, monitors, scoreboards, agents, and sequences
- Contribute to the creation and execution of verification plans based on design specifications and architec...
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