Job Description

  • As a member of the Design Verification [Pre-Silicon DV] .
  • You will be responsible for verification of various IP's and/or SoC.
  • Candidate must be self-motivated and capable of working independently or as part of a team.
  • You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
  • You will also assist with developing test-plans, debugging failures and analyzing coverage information.
  • Must have excellent knowledge of computer architecture and design verification fundamentals
  • Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
  • Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology
  • Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol
  • Experienc...

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