Job Description
We are seeking a skilled and motivated
Design Verification Engineer (DV)
with expertise in Ethernet protocols, MAC layer functionality, and RoCE (RDMA over Converged Ethernet). The ideal candidate will have hands-on experience with
Synopsys Ethernet PHY and controller IPs , and a strong understanding of high-performance networking technologies.
Key Responsibilities
Develop and execute verification plans for Ethernet MAC and PHY IP blocks
Design and implement testbenches using industry-standard methodologies (UVM, SystemVerilog)
Validate RoCE protocol implementations for low-latency, high-throughput data transfer
Collaborate with design and architecture teams to ensure functional correctness and performance
Debug and resolve issues across simulation and emulation platforms
Contribute to coverage analysis and closure
Preferred Qualifications
Strong knowledge of
Ethernet protocols , including MAC layer operations
Design Verification Engineer (DV)
with expertise in Ethernet protocols, MAC layer functionality, and RoCE (RDMA over Converged Ethernet). The ideal candidate will have hands-on experience with
Synopsys Ethernet PHY and controller IPs , and a strong understanding of high-performance networking technologies.
Key Responsibilities
Develop and execute verification plans for Ethernet MAC and PHY IP blocks
Design and implement testbenches using industry-standard methodologies (UVM, SystemVerilog)
Validate RoCE protocol implementations for low-latency, high-throughput data transfer
Collaborate with design and architecture teams to ensure functional correctness and performance
Debug and resolve issues across simulation and emulation platforms
Contribute to coverage analysis and closure
Preferred Qualifications
Strong knowledge of
Ethernet protocols , including MAC layer operations
Ready to Apply?
Take the next step in your AI career. Submit your application to Sintegra Inc. today.
Submit Application