Job Description
**Position:**
Design Verification Engineer III
**Job Description:**
**What You'll Be Doing:** **Candidate roles and responsibilities:**
+ Responsible for analyzing and capturing requirements, Functional Testplan development, Verification plan development related to Consumer Electronics and AI ASICs, Mixed Signal ASICs
+ Responsible to create reusable verification environment in System Verilog, UVM (Universal Verification Methodology) based on the strategy using Ethernet UVM VIPs and models. Verification environment include creating testbench, integrating DUT (Design under Test) with testbench, integrating the third-party VIP (Verification Intellectual Property), creating verification components such as drivers, monitors, checkers etc, integrating the created IUVCs (Interface UVM Components) in testbench.
+ Complex corner case scenarios development for thorough verification
+ Responsible for signing off on the throughput and BW analysis of end-to...
Design Verification Engineer III
**Job Description:**
**What You'll Be Doing:** **Candidate roles and responsibilities:**
+ Responsible for analyzing and capturing requirements, Functional Testplan development, Verification plan development related to Consumer Electronics and AI ASICs, Mixed Signal ASICs
+ Responsible to create reusable verification environment in System Verilog, UVM (Universal Verification Methodology) based on the strategy using Ethernet UVM VIPs and models. Verification environment include creating testbench, integrating DUT (Design under Test) with testbench, integrating the third-party VIP (Verification Intellectual Property), creating verification components such as drivers, monitors, checkers etc, integrating the created IUVCs (Interface UVM Components) in testbench.
+ Complex corner case scenarios development for thorough verification
+ Responsible for signing off on the throughput and BW analysis of end-to...
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