Job Description

Key Responsibility

  • Write and debug test cases to ensure functional correctness of RTL.
  • Perform code and functional coverage analysis and drive coverage closure.
  • Participate in regression testing and continuous integration workflows.
  • Document verification results and maintain traceability to requirements.

Required Skills

  • 0–1 years of hands-on experience in digital design verification.
  • Proficiency in SystemVerilog, UVM, and scripting languages (e.g., Python, Perl, Tcl).
  • Good understanding of digital design concepts, RTL, and simulation tools (e.g., VCS, Questa, XSIM).
  • Experience with coverage-driven verification and assertion-based verification.
  • Familiarity with version control systems and bug tracking tools.
  • Strong problem-solving and debugging skills.
  • Excellent communication and teamwork abilities.
  • Exposure to...

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