Design Verification (DV) Engineer

Job Summary

We are seeking an IP DV Engineer with significant hands‑on experience in pre‑silicon Design verification, verification methodologies, and UVM/OVM. The role involves developing test plans, building constrained‑random verification environments, and driving coverage completion.

Responsibilities

• Develop and review test plans based on design specifications.
• Create constrained‑random verification environments for complex DUTs.
• Implement coverage metrics using cover points and assertions.
• Write and debug tests for DUTs.
• Resolve bugs in collaboration with remote designers.

Qualifications

• Strong understanding of the verification process from test plan to coverage completion.
• Excellent communication and analytical skills.
• Proficiency in HDL (Verilog, SystemVerilog).
• Programming skills (C/C++, Perl, TCL, or Python).
• Experience with FPGA design is a pl...