Design Engineer II Cadence

Overview

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.

The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality.

Responsibilities

The candidate will primarily be responsible for the verification of digital RTL and development of reusable verification components and environments.

It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.

Qualifications

The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members o...