Job Description
JOB DUTIES: Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails, and developing and analyzing functional coverage on North Bridge / Data Fabric Design. Key skills are software (System Verilog, C/C++, object oriented programming, scripting (e.g. Perl), x86 assembly), Verilog simulation and modeling, knowledge of computer and peripheral architectures. EXPERIENCE AND EDUCATION:Bachelors and 8-10 years experience, or Masters and 8+ years experience;Requires demonstrated technical expertise in functional verification of microprocessor desig
The Cyber Security Engineer 2 is responsible for supporting and enhancing the organization’s endpoint security posture through a c...
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