Job Description

About the role

  • You will own end-to-end compilation pipelines from high-level ML graph representations down to optimized target execution
  • Get the opportunity to design and implement passes for operator fusion, memory layout transformation, and tiling across compute hierarchies
  • You will build lowering infrastructure that bridges framework-level IR (MLIR, XLA, or equivalent) to hardware-specific backends
  • You will be responsible for profiling and closing performance gaps between theoretical and achieved hardware utilization
  • You will have the chance to collaborate directly with pioneering hardware architects to co-design compiler primitives that expose silicon capabilities
  • You’ll contribute to the tooling that lets researchers iterate fast without sacrificing production-level efficiency

Key requirements

  • You're experienced working with compilers, particularly on IR design or optimization p...

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