Job Description

  • M.S. in Electrical Engineering or Microelectronics.
  • At least 3 years of experience in Pre-Silicon verification.
  • Knowledge in UVM methodology - advantage.
  • Proficiency in python/perl/tcl/shell - must (one of them).
  • Prefer experience with chip CP/FT test.
  • Prefer experience with management capabilities is PLUS
  • Participate in IP and system-level simulation verification.
  • Based on architectural documentation, construct a verification environment using UVM. and env maintenance.
  • Define rational functional coverage targets, Improve code coverage and functional coverage base-on verification plan.
  • Verification experience with gate-sim and post-sim - must Case fix, complete verification tasks at each deliver stage, meet validation requirements at each milestone and support tape-out
  • Undertake chip verification work for new products.

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