ASIC Design Verification Engineer – UVM & Formal

A technology company is seeking an experienced ASIC Design Verification Engineer in Ottawa, Ontario. The ideal candidate will develop testbenches, analyze coverage, and utilize automation for design verification activities. Proficiency in Verilog, System Verilog, and UVM is essential. Candidates should demonstrate strong analytical thinking and problem-solving skills, along with effective communication abilities. This role offers the opportunity to work within a collaborative and innovative environment focused on cutting-edge technology.
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