ASIC Design Engineer_3INR

Title: ASIC Engineer 3_INR

Experience: 5-8 Years

Location: Hyderabad

Description:

The team member will typically work on processors, controller architectures or ASICs for Enterprise SSD Group. Should be proficient in block level low power aware floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tape out activities.

Requirements

5-8 years of hands-on physical design implementation experience along with APR flow development and PPA analysis

STA closure at block

Experience in Advanced process technology nodes (6/7 nm preferred)

Experience with Cadence layout tools (Innovus, Tempus, etc..)

Hands on work experience in Physical verification closure (DRC/LVS/Antenna) with Caliber tool

Experience in closing all the IR issues within the block based on feedback

Should be strong in fundamentals of digital electronics and mi...