Analog Layout Design Engineer

Job Title:Analog Layout Engineer – Advanced / Lower Nodes (TSMC)
Experience:4 -7 Years
Location: Hyderabad (F2F)

Job Summary
We are seeking an experienced Analog Layout Engineer to design and implement high-performance analog and mixed-signal IC layouts in advanced CMOS technology nodes (e.g., 28nm, 16nm, 7nm, 5nm, 3nm) at TSMC. The role requires close collaboration with analog design, verification, and foundry teams to ensure robust, manufacturable, and high-yield layouts.
Key Responsibilities
Design and deliver

full-custom analog and mixed-signal layouts

for advanced TSMC technology nodes
Handle layout of blocks such as

LDOs, PLLs, ADC/DACs, SerDes, amplifiers, bandgaps, clocking, and IOs
Apply

advanced layout techniques :
Matching, symmetry, common-centroid, interdigitation
Guard rings, shielding, substrate isolation
EM/IR-aware routing and reliability-driven layout
Ensure compliance with

TSMC DRC...