Job Description

Senior Analog IC Layout Engineer
  • Experienced analog IC layout,
  • Coarse geometry, 0.35um CMOS
  • Experience in Cadence tools , ASSURA DRC LVS , PVS DRC LVS, and QRC
  • Experience in Mentor Calibre Tools DRC LVS and Parasitic Extraction

    • Ready to Apply?

    Take the next step in your AI career. Submit your application to Chipright today.

    Submit Application