Advanced Node Interface Architect

Job Summary

Seeking an Analog Design Engineer with 5–10 years of experience in high‑speed I/O circuit design to develop high‑performance analog and mixed‑signal IPs. The role involves architecture definition, circuit design, simulation, and silicon validation for advanced‑node high‑speed interfaces.

Key Responsibilities

• Work on High‑Speed I/O and SerDes PHY design, including PLLs, CDRs, equalizers, and multi‑Gbps analog blocks.
• Design/optimize TX/RX front‑ends, PLL/DLL/CDR circuits, equalization (CTLE/DFE/FFE), and bias/termination/ESD structures.
• Lead block‑level architecture and circuit development for high‑speed I/O subsystems.
• Run transistor‑level simulations (AC, transient, noise, jitter, BER).
• Handle pre‑layout and post‑layout verification with parasitic extraction.
• Address signal integrity issues such as channel loss, crosstalk, and reflections.
• Support layout floorplannin...